This invention relates to the field of memory circuit design and more specifically, to address decoder circuitry for use in memory circuits.
The basic building block of a memory circuit is a memory cell capable of storing a single binary digit ("bit") of information. FIG. 1 is a block diagram of a typical read-only memory (ROM) constructed with a matrix of memory cells. Data is stored in memory cells 3-1-1 through 3-4-4, which are arranged in a matrix having four rows and four columns. The memory cell which provides an output signal on output terminal 6 is selected by address input signals A.sub.0 through A.sub.3. For example, if it is desired to provide the data stored in memory cell 3-2-2 on output terminal 6, then input signals A.sub.0 and A.sub.1 are provided which cause address decoder 1 to provide a logical 1 (approximately 5 volts) on selected row 4-2 and provide a logical 0 (approximately 0 volts) on deselected rows 4-1, 4-3, and 4-4. The logical 1 on row 4-2 causes cells 3-1-2 through 3-4-2 to provide output signals representing stored data on column leads 5-1 through 5-4, respectively. Input signals A.sub.2 and A.sub.3 are provided to multiplexer 2 in order to select a desired one of columns 5-1 through 5-4, 5-2 to output terminal 6 in this example, providing an output signal on output terminal 6 corresponding to the data stored in memory cell 3-2-2.
A simple address decoder such as decoder 1 is shown in FIG. 2. Address input signals A, B, C, and D are provided to inverters 32, 33, 34, and 35 which provide inverted signals A, B, C, and D, respectively. A is the most significant bit. D is the least significant bit of the input signal. AND gate 31 receives as input signals input signal A, input signal B, input signal C, and input signal D. Thus, AND gate 31 provides a logical 1 output signal on output terminal 31-1 when the binary number 1100 is provided by input signals A, B, C, and D. To complete the decoder, 15 other AND gates similar to AND gate 31 are provided; each AND gate is associated with a unique numerical value of the binary number provided by input signals A, B, C, and D. Naturally, if desired, AND gate 31 can be replaced by a NAND gate and a buffer inverter for providing a buffered output signal on output terminal 31-1.
A schematic diagram of a Complementary Metal Oxide Semiconductor (CMOS) implementation of AND gate 31 is shown in FIG. 3. Of importance, AND gate 31 requires eight transistors. A schematic diagram of inverter 32 (FIG. 2) implemented in CMOS is shown in FIG. 4. CMOS inverter 32 requires two transistors. Thus, a complete decoder constructed using the principals shown in FIG. 2 requires 4 inverters and 16 AND gates which, when implemented in CMOS, requires 132 transistors. This requires a rather substantial amount of area in an integrated circuit device.
Some examples of prior art methods for providing memory decoding using MOS transistors which are physically smaller than decoder 30 are Perlegos, et al., U.S. Pat. No. 4,094,012, entitled "Electrically Programmable MOS Read-Only Memory with Isolated Decoders", issued June 6, 1978, Kawagoe, U.S. Pat. No. 4,240,151, entitled "Semiconductor Read-Only Memory", issued Dec. 16, 1980, Moench, U.S. Pat. No. 4,259,731, entitled "Quiet Row Selection Circuitry", issued Mar. 31, 1981, Perlegos, et al., U.S. Pat. No. 4,264,828, entitled "MOS Static Decoding Circuit", issued Apr. 28, 1981, Saitou, et al., U.S. Pat. No. 4,275,312, entitled "MOS Decoder Logic Circuit Having Reduced Power Consumption", issued June 23, 1981, Suzuki, et al., U.S. Pat. No. 4,455,629, entitled "Complementary Metal-Insulated Semiconductor Memory Decoder", issued June 19, 1984, which are hereby incorporated by reference. The structures of the referenced patents share a problem of high power consumption because of their N-channel Metal-Oxide Semiconductor (NMOS) designs. In addition, the above-referenced patents require specific memory matrix design in order to properly operate rather than providing a general circuit capable of providing the appropriate signals to several types of memory circuitry. A bipolar implementation of a decoder circuit is shown in Fukushima, et al., U.S. Pat. No. 4,347,584, entitled "Programmable Read-Only Memory Device", issued Aug. 31, 1982, which is hereby incorporated by reference. The device of Fukushima, et al., shares the problem of excess power consumption and, in addition, is slow due to the use of PNP bipolar transistors.